آموزش طراحی VLSI CAD بخش دوم: چیدمان (Layout) - آخرین آپدیت

Orientation Orientation

• Welcome and Introduction Welcome and Introduction

• Two Tools Tutorial Two Tools Tutorial

ASIC Placement ASIC Placement

• Basics Basics

• Wirelength Estimation Wirelength Estimation

• Simple Iterative Improvement Placement Simple Iterative Improvement Placement

• Iterative Improvement with Hill Climbing Iterative Improvement with Hill Climbing

• Simulated Annealing Placement Simulated Annealing Placement

• Analytical Placement: Quadratic Wirelength Model Analytical Placement: Quadratic Wirelength Model

• Analytical Placement: Quadratic Placement Analytical Placement: Quadratic Placement

• Analytical Placement: Recursive Partitioning Analytical Placement: Recursive Partitioning

• Analytical Placement: Recursive Partitioning Example Analytical Placement: Recursive Partitioning Example

Technology Mapping Technology Mapping

• Technology Mapping Basics Technology Mapping Basics

• Technology Mapping as Tree Covering Technology Mapping as Tree Covering

• Technology Mapping—Tree ifying the Netlist Technology Mapping—Tree-ifying the Netlist

• Technology Mapping—Recursive Matching Technology Mapping—Recursive Matching

• Technology Mapping—Minimum Cost Covering Technology Mapping—Minimum Cost Covering

• Technology Mapping—Detailed Covering Example Technology Mapping—Detailed Covering Example

ASIC Routing ASIC Routing

• Routing Basics Routing Basics

• Maze Routing: 2 Point Nets in 1 Layer Maze Routing: 2-Point Nets in 1 Layer

• Maze Routing: Multi Point Nets Maze Routing: Multi-Point Nets

• Maze Routing: Multi Layer Routing Maze Routing: Multi-Layer Routing

• Maze Routing: Non Uniform Grid Costs Maze Routing: Non-Uniform Grid Costs

• Implementation Mechanics: How Expansion Works Implementation Mechanics: How Expansion Works

• Implementation Mechanics: Data Structures &Constraints Implementation Mechanics: Data Structures & Constraints

• Implementation Mechanics: Depth First Search Implementation Mechanics: Depth First Search

• From Detailed Routing to Global Routing From Detailed Routing to Global Routing

Timing Analysis Timing Analysis

• Basics Basics

• Logic Level Timing: Basic Assumptions &Models Logic-Level Timing: Basic Assumptions & Models

• Logic Level Timing: STA Delay Graph, ATs, RATs, and Slacks Logic-Level Timing: STA Delay Graph, ATs, RATs, and Slacks

• Logic Level Timing: A Detailed Example and the Role of Slack Logic-Level Timing: A Detailed Example and the Role of Slack

• Logic Level Timing: Computing ATs, RATs, Slacks, and Worst Paths Logic-Level Timing: Computing ATs, RATs, Slacks, and Worst Paths

• Interconnect Timing: Electrical Models of Wire Delay Interconnect Timing: Electrical Models of Wire Delay

• Interconnect Timing: The Elmore Delay Model Interconnect Timing: The Elmore Delay Model

• Interconnect Timing: Elmore Delay Examples Interconnect Timing: Elmore Delay Examples

Final Exam Final Exam