آموزش مبانی معماری کامپیوتر در فناوری Arm - آخرین آپدیت

Module 1: Fundamentals of Computer Design Module 1: Fundamentals of Computer Design

• About the Course About the Course

• Why Study Computer Architecture? Why Study Computer Architecture?

• Meet the Authors Meet the Authors

• An Introduction to the World of Computer Architecture An Introduction to the World of Computer Architecture

• KV1(1)What is Computer Architecture? KV1(1)What is Computer Architecture?

• KV2 (1) What is the Fetch Execute Cycle? KV2 (1) What is the Fetch-Execute Cycle?

• KV3 (1) What Are the Basic Components of a Microprocessor? KV3 (1) What Are the Basic Components of a Microprocessor?

• KV4(1) How Do You Tell a Microprocessor What to Do? KV4(1) How Do You Tell a Microprocessor What to Do?

• SV1(1) Lab Project: Fundamentals of Computer Design SV1(1) Lab Project: Fundamentals of Computer Design

Module 2: Pipelining Module 2: Pipelining

• Designing a Computer Architecture Designing a Computer Architecture

• KV1(2): The Processor Performance Equation KV1(2): The Processor Performance Equation

• KV2 (2) Pipelining a Microprocessor KV2 (2) Pipelining a Microprocessor

• KV3 (2) Hazards KV3 (2) Hazards

• KV4 (2) The Limits of Pipelining KV4 (2) The Limits of Pipelining

• SV1 (2) Lab Project: Pipelining SV1 (2) Lab Project: Pipelining

Module 3: Handling Branches Module 3: Handling Branches

• An Introduction to Instructure Set Architecture (ISA) An Introduction to Instructure Set Architecture (ISA)

• KV1 (3) Avoiding Stalls Due to Control Dependencies KV1 (3) Avoiding Stalls Due to Control Dependencies

• KV2 (3) Dynamic Branch Prediction KV2 (3) Dynamic Branch Prediction

• KV3 (3) Branch Predictors KV3 (3) Branch Predictors

• KV4 (3) Limits to Branch Prediction KV4 (3) Limits to Branch Prediction

• SV1 (3) Lab Project: Handling Branches SV1 (3) Lab Project: Handling Branches

Module 4: Cache Memories Module 4: Cache Memories

• KV1 (4) The Purpose of Cache Memories KV1 (4) The Purpose of Cache Memories

• KV2 (4) Patterns that Caches Exploit KV2 (4) Patterns that Caches Exploit

• KV3 (4) The Construction of a Cache KV3 (4) The Construction of a Cache

• KV4 (4) How Do We Measure Cache Performance? KV4 (4) How Do We Measure Cache Performance?

• SV1 (4) Lab Project: Cache Memories SV1 (4) Lab Project: Cache Memories

Module 5: Superscalar Processors Module 5: Superscalar Processors

• KV1 (5) Instruction Level Parallelism KV1 (5) Instruction-Level Parallelism

• KV2 (5) A Simple Superscalar Processor KV2 (5) A Simple Superscalar Processor

• KV3 (5) The Limits of Instruction Level Parallelism KV3 (5) The Limits of Instruction-Level Parallelism

• SV1 (5) Lab Project: Superscalar Processes SV1 (5) Lab Project: Superscalar Processes

Module 6: Out of Order Execution Module 6: Out-of-Order Execution

• W (6) Complex Processors W (6) Complex Processors

• KV1 (6) Register Renaming KV1 (6) Register Renaming

• KV2 (6) Speculative Execution KV2 (6) Speculative Execution

• KV3 (6) An Out of Order Superscalar Pipeline KV3 (6) An Out-of-Order Superscalar Pipeline

• KV4 (6) The Limits of Superscalar Processors KV4 (6) The Limits of Superscalar Processors

• SV1 (6) Lab Project: Out of Order Execution SV1 (6) Lab Project: Out-of-Order Execution

• Inspirational Advice Inspirational Advice